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features ? high-performance, low-power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions ? mo st single-clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20mips throughput at 20mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 16/32/64/128kbytes of in-system self -programmable flash program memory ? 512/1k/2k/4kbytes eeprom ? 1/2/4/16kbytes internal sram ? write/erase cycles: 10,000 flash/ 100,000 eeprom ? data retention: 20 years at 85 c/ 100 years at 25 c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? programming lock for software security ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? qtouch and qmatrix acquisition ? up to 64 sense channels ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities acco rding to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits throug h the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescalers and compare modes ? one/two 16-bit timer/counter with separa te prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel, 10-bit adc differential mode with selectable gain at 1x, 10x or 200x ? byte-oriented two-wire serial interface ? two programmable serial usart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcon troller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby and extended standby ? i/o and packages ? 32 programmable i/o lines ? 40-pin pdip, 44-lead tqfp, 44-pad vqfn/qfn/mlf ? 44-pad drqfn ? 49-ball vfbga ? operating voltages ? 1.8 - 5.5v ? speed grades ? 0 - 4mhz @ 1.8 - 5.5v ? 0 - 10mhz @ 2.7 - 5.5v ? 0 - 20mhz @ 4.5 - 5.5v ? power consumption at 1mhz, 1.8v, 25 c ? active: 0.4ma ? power-down mode: 0.1a ? power-save mode: 0.6a (including 32khz rtc) note: 1. see ?data retention? on page 9 for details. 8-bit atmel microcontroller with 16/32/64/128k bytes in-system programmable flash atmega164a atmega164pa atmega324a atmega324pa ATMEGA644A atmega644pa atmega1284 atmega1284p summary 8272cs?avr?06/11
2 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 1. pin configurations 1.1 pinout - pdip/tqfp /vqfn/qfn/mlf for atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p figure 1-1. pinout note: the large center pad underneath the vqfn/qfn/mlf package should be soldered to ground on the board to ensure good mechanical stability. (pcint8/xck0/t0) pb0 (pcint9/clko/t1) pb1 (pcint10/int2/ain0) pb2 (pcint11/oc0a/ain1) pb3 (pcint12/oc0b/ss) pb4 (pcint13/icp3/mosi) pb5 (pcint14/oc3a/miso) pb6 (pcint15/oc3b/sck) pb7 reset vcc gnd xtal2 xtal1 (pcint24/rxd0/t3) pd0 (pcint25/txd0) pd1 (pcint26/rxd1/int0) pd2 (pcint27/txd1/int1) pd3 (pcint28/xck1/oc1b) pd4 (pcint29/oc1a) pd5 (pcint30/oc2b/icp) pd6 pa0 (adc0/pcint0) pa1 (adc1/pcint1) pa2 (adc2/pcint2) pa3 (adc3/pcint3) pa4 (adc4/pcint4) pa5 (adc5/pcint5) pa6 (adc6/pcint6) pa7 (adc7/pcint7) aref gnd avcc pc7 (tosc2/pcint23) pc6 (tosc1/pcint22) pc5 (tdi/pcint21) pc4 (tdo/pcint20) pc3 (tms/pcint19) pc2 (tck/pcint18) pc1 (sda/pcint17) pc0 (scl/pcint16) pd7 (oc2a/pcint31) pa4 (adc4/pcint4) pa5 (adc5/pcint5) pa6 (adc6/pcint6) pa7 (adc7/pcint7) aref gnd avcc pc7 (tosc2/pcint23) pc6 (tosc1/pcint22) pc5 (tdi/pcint21) pc4 (tdo/pcint20) (pcint13/icp3/mosi) pb5 (pcint14/oc3a/miso) pb6 (pcint15/oc3b/sck) pb7 reset vcc gnd xtal2 xtal1 (pcint24/rxd0/t3) pd0 (pcint25/txd0) pd1 (pcint26/rxd1/int0) pd2 (pcint27/txd1/int1) pd3 (pcint28/xck1/oc1b) pd4 (pcint29/oc1a) pd5 (pcint30/oc2b/icp) pd6 (pcint31/oc2a) pd7 vcc gnd (pcint16/scl) pc0 (pcint17/sda) pc1 (pcint18/tck) pc2 (pcint19/tms) pc3 pb4 (ss/oc0b/pcint12) pb3 (ain1/oc0a/pcint11) pb2 (ain0/int2/pcint10) pb1 (t1/clko/pcint9) pb0 (xck0/t0/pcint8) gnd vcc pa0 (adc0/pcint0) pa1 (adc1/pcint1) pa2 (adc2/pcint2) pa3 (adc3/pcint3) tqfp/qfn/mlf
3 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 1.2 pinout - drqfn for at mega164a/164pa/324a/324pa figure 1-2. drqfn - pinout table 1-1. drqfn - pinout a1 pb5 a7 pd3 a13 pc4 a19 pa 3 b1 pb6 b6 pd4 b11 pc5 b16 pa 2 a2 pb7 a8 pd5 a14 pc6 a20 pa 1 b2 reset b7 pd6 b12 pc7 b17 pa 0 a3 vcc a9 pd7 a15 avcc a21 vcc b3 gnd b8 vcc b13 gnd b18 gnd a4 xtal2 a10 gnd a16 aref a22 pb0 b4 xtal1 b9 pc0 b14 pa 7 b19 pb1 a5 pd0 a11 pc1 a17 pa 6 a23 pb2 b5 pd1 b10 pc2 b15 pa 5 b20 pb3 a6 pd2 a12 pc3 a18 pa 4 a24 pb4 top view bottom view a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 a18 b15 a17 b14 a16 b13 a15 b12 a14 b11 a13 a12 b10 a11 b9 a10 b8 a9 b7 a8 b6 a7 a24 b20 a23 b19 a22 b18 a21 b17 a20 b16 a19 a18 b15 a17 b14 a16 b13 a15 b12 a14 b11 a13 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 a7 b6 a8 b7 a9 b8 a10 b9 a11 b10 a12 a19 b16 a20 b17 a21 b18 a22 b19 a23 b20 a24
4 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 1.3 pinout - vfbga for at mega164a/164pa/324a/324pa figure 1-3. vfbga - pinout table 1-2. bga - pinout 1234567 a gnd pb4 pb2 gnd vcc pa2 gnd b pb6 pb5 pb3 pb0 pa0 pa3 pa5 c vcc reset pb7 pb1 pa1 pa6 aref d gnd xtal2 pd0 gnd pa4 pa7 gnd e xtal1 pd1 pd5 pd7 pc5 pc7 avcc f pd2 pd3 pd6 pc0 pc2 pc4 pc6 g gnd pd4 vcc gnd pc1 pc3 gnd a b c d e f g 1 234567 a b c d e f g 765432 1 top view bottom view
5 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 2. overview the atmega164a/164pa/324a/324pa/644a/644pa/ 1284/1284p is a low-power cmos 8-bit microcontroller based on the avr enhanced risc ar chitecture. by executing powerful instruc- tions in a single clock cycle, the atmega 164a/164pa/324a/324pa/644a/644pa/1284/1284p achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. cpu gnd vcc reset power supervision por / bod & reset watchdog oscillator watchdog timer oscillator circuits / clock generation xtal1 xtal2 port a (8) port d (8) pd7..0 port c (8) pc5..0 twi spi eeprom jtag/ocd 16bit t/c 1 8bit t/c 2 8bit t/c 0 sram flash usart 0 internal bandgap reference analog comparator a/d converter pa7..0 port b (8) pb7..0 usart 1 tosc1/pc6 tosc2/pc7 16bit t/c 1 16bit t/c 3
6 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p provide the following features: 16/32/64/128kbytes of in-s ystem programmable flash with read-while-write capabilities, 512/1k/2k/4kbyt es eeprom, 1/2/4/16kbytes sram, 32 general purpose i/o lines, 32 general purpose working registers, real time counter (r tc), three flexible timer/counters with com- pare modes and pwm, 2 usarts, a byte oriented 2-wire serial interface, a 8-channel, 10-bit adc with optional differential input stage with programmable gain, programmable watchdog timer with internal oscilla tor, an spi serial port, ieee std. 114 9.1 compliant jtag test interface, also used for accessing the on-chip debug system and programming and six software select- able power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscilla tor, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i /o modules except asynchronous timer and adc, to minimize switching noise during adc co nversions. in standby mode, the crystal/reso- nator oscillator is running while the rest of the dev ice is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. atmel offers the qtouch ? library for embedding capacitive t ouch buttons, sliders and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high- density nonvolatile memory technology. the on- chip isp flash allows the prog ram memory to be repr ogrammed in-system th rough an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the applicatio n flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega164a/164pa/324a/324pa/644a /644pa/1284/1284p is a powerful microcon- troller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p is supported with a full suite of program and system development tools includin g: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
7 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 2.2 comparison between at mega164a, atmega164pa, at mega324a, atmega324pa, ATMEGA644A, atmega644pa, atmega1284 and atmega1284p 2.3 pin descriptions 2.3.1 vcc digital supply voltage. 2.3.2 gnd ground. 2.3.3 port a (pa7:pa0) port a serves as analog inputs to the analog-to-digital converter. port a also serves as an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetr ical drive characterist ics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p as listed on page 80 . 2.3.4 port b (pb7:pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p as listed on page 82 . 2.3.5 port c (pc7:pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source table 2-1. differences between atmega164a, atmega164pa, atmega324a, atmega324pa, ATMEGA644A, atmega644pa, atmega1284 and atmega1284p device flash eeprom ram units atmega164a 16 k 512 1 k bytes atmega164pa 16 k 512 1 k atmega324a 32 k 1 k 2 k atmega324pa 32 k 1 k 2 k ATMEGA644A 64 k 2 k 4 k atmega644pa 64 k 2 k 4 k atmega1284 128 k 4 k 16 k atmega1284p 128 k 4 k 16 k
8 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of the jtag interface, along with special features of the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p as listed on page 85 . 2.3.6 port d (pd7:pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega164a/164pa/324a/324pa/644a/644pa/1284/1284p as listed on page 88 . 2.3.7 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not runni ng. the minimum pulse length is given in ?system and reset characteristics? on page 337 . shorter pulses are not guaranteed to generate a reset. 2.3.8 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.3.9 xtal2 output from the invert ing oscillator amplifier. 2.3.10 avcc avcc is the supply voltage pin for port a and the analog-to-digital converter. it should be exter- nally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.3.11 aref this is the analog reference pin for the analog-to-digital converter.
9 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 3. resources a comprehensive set of development tools, application notes and datasheetsare available for download on http:// www.atmel.com/avr. 4. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. the code examples assume that the part specific header file is included before compilation. for i/o registers located in extended i/o map, "in", "out", "sbis", "sbic", "cbi", and "sbi" instruc- tions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbrc", "sbr", and "cbr". note: 1. 5. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 6. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use solution to realize touch sensitive inter- faces on most atmel avr ? microcontrollers. the qtouch library includes support for the qtouch and qmatrix ? acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
10 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 7. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved - - - - - - - - (0xfb) reserved - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved - - - - - - - - (0xf5) reserved - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved - - - - - - - - (0xf1) reserved - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved - - - - - - - - (0xeb) reserved - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved - - - - - - - - (0xe3) reserved - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - (0xe0) reserved - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) reserved - - - - - - - - (0xdc) reserved - - - - - - - (0xdb) reserved - - - - - - - - (0xda) reserved - - - - - - - - (0xd9) reserved - - - - - - - - (0xd8) reserved - - - - - - - - (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) udr1 usart1 i/o data register 192 (0xcd) ubrr1h - - - - usart1 baud rate register high byte 196 / 209 (0xcc) ubrr1l usart1 baud rate register low byte 196 / 209 (0xcb) reserved - - - - - - - - (0xca) ucsr1c umsel11 umsel10 u pm11 upm10 usbs1 ucsz11/udord0 (5) ucsz10/ucpha0 (5) ucpol1 194 / 208 (0xc9) ucsr1b rxcie1 txcie1 udri e1 rxen1 txen1 ucsz12 rxb81 txb81 193 / 207 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 192 / 207 (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 i/o data register 192 (0xc5) ubrr0h - - - - usart0 baud rate register high byte 196 / 209 (0xc4) ubrr0l usart0 baud rate register low byte 196 / 209 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c umsel01 umsel00 u pm01 upm00 usbs0 ucsz01/udord0 (5) ucsz00/ucpha0 (5) ucpol0 194 / 208 (0xc1) ucsr0b rxcie0 txcie0 udri e0 rxen0 txen0 ucsz02 rxb80 txb80 193 / 207
11 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 192 / 207 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 - 238 (0xbc) twcr twint twea twsta twsto twwc twen -twie 235 (0xbb) twdr 2-wire serial interface data register 237 (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 238 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 - twps1 twps0 237 (0xb8) twbr 2-wire serial interface bit rate register 235 (0xb7) reserved - - - - - - - - (0xb6) assr - exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 161 (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b 160 (0xb3) ocr2a timer/counter2 output compare register a 160 (0xb2) tcnt2 timer/counter2 (8 bit) 160 (0xb1) tccr2b foc2a foc2b - - wgm22 cs22 cs21 cs20 159 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - -wgm21wgm20 156 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) ocr3bh timer/counter3 - output compare register b high byte 137 (0x9a) ocr3bl timer/counter3 - output compare register b low byte 137 (0x99) ocr3ah timer/counter3 - output compare register a high byte 136 (0x98) ocr3al timer/counter3 - output compare register a low byte 136 (0x97) icr3h timer/counter3 - input capture register high byte 137 (0x96) icr3l timer/counter3 - input capture register low byte 137 (0x95) tcnt3h timer/counter3 - counter register high byte 136 (0x94) tcnt3l timer/counter3 - counter register low byte 136 (0x93) reserved - - - - - - - - (0x92) tccr3c foc3a foc3b - - - - - - 135 (0x91) tccr3b icnc3 ices3 - wgm33 wgm32 cs32 cs31 cs30 134 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 - -wgm31wgm30 132 (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 - output compare register b high byte 137 (0x8a) ocr1bl timer/counter1 - output compare register b low byte 137 (0x89) ocr1ah timer/counter1 - output compare register a high byte 136 (0x88) ocr1al timer/counter1 - output compare register a low byte 136 (0x87) icr1h timer/counter1 - input capture register high byte 137 (0x86) icr1l timer/counter1 - input capture register low byte 137 (0x85) tcnt1h timer/counter1 - counter register high byte 136 (0x84) tcnt1l timer/counter1 - counter register low byte 136 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b - - - - - - 135 (0x81) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 134 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 - -wgm11wgm10 132 (0x7f) didr1 - - - - - -ain1dain0d 242 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 262 (0x7d) reserved - - - - - - - - (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 258 (0x7b) adcsrb -acme - - - adts2 adts1 adts0 241 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 260 (0x79) adch adc data register high byte 261 (0x78) adcl adc data register low byte 261 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - (0x75) reserved - - - - - - - - (0x74) reserved - - - - - - - - (0x73) pcmsk3 pcint31 pcint30 pcint29 p cint28 pcint27 pcint26 pcint25 pcint24 70 (0x72) reserved - - - - - - - - (0x71) timsk3 - -icie3 - - ocie3b ocie3a toie3 139 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 162 (0x6f) timsk1 - -icie1 - - ocie1b ocie1a toie1 138 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 109 (0x6d) pcmsk2 pcint23 pcint22 pcint21 p cint20 pcint19 pcint18 pcint17 pcint16 70 (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 70 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 71 (0x6a) reserved - - - - - - - - (0x69) eicra - - isc21 isc20 isc11 isc10 isc01 isc00 67 (0x68) pcicr - - - - pcie3 pcie2 pcie1 pcie0 69 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register 40 (0x65) reserved - - - - - - - - (0x64) prr prtwi prtim2 prtim0 prusart1 prtim1 prspi prusart0 pradc 48 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 40 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 59 0x3f (0x5f) sreg i t h s v n z c 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) reserved - - - - - - - - 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 295 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd bods (6) bodse (6) pud - - ivsel ivce 91 / 278 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 58 / 278 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 47 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr on-chip debug register 268 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 260 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi 0 data register 173 0x2d (0x4d) spsr spif0 wcol0 - - - - -spi2x0 172 0x2c (0x4c) spcr spie0 spe0 do rd0 mstr0 cpol0 cp ha0 spr01 spr00 171 0x2b (0x4b) gpior2 general purpose i/o register 2 29 0x2a (0x4a) gpior1 general purpose i/o register 1 29 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) ocr0b timer/counter0 output compare register b 108 0x27 (0x47) ocr0a timer/counter0 output compare register a 108 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 108 0x25 (0x45) tccr0b foc0a foc0b - - wgm02 cs02 cs01 cs00 107 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - -wgm01wgm00 108 0x23 (0x43) gtccr tsm - - - - - psrasy psrsync 163 0x22 (0x42) eearh - - - - eeprom address register high byte 24 0x21 (0x41) eearl eeprom address register low byte 24 0x20 (0x40) eedr eeprom data register 24 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere 24 0x1e (0x3e) gpior0 general purpose i/o register 0 29 0x1d (0x3d) eimsk - - - - - int2 int1 int0 68 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag r ead as set, thus clearing the fl ag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o regis- ters as data space using ld and st instructions, $20 must be added to these addresses. the atmega164a/164pa/324a/324pa/644a/644p a/1284/1284p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out inst ructions. for the extended i/o space from $60 - $ff , only the st/sts/std and ld/lds /ldd instructions can be used. 5. usart in spi master mode. 6. only available in the atmega164pa/324pa/644pa/1284p. 0x1c (0x3c) eifr - - - - - intf2 intf1 intf0 68 0x1b (0x3b) pcifr - - - - pcif3 pcif2 pcif1 pcif0 69 0x1a (0x3a) reserved - - - - - - - - 0x19 (0x39) reserved - - - - - - - - 0x18 (0x38) tifr3 - -icf3 - -ocf3b ocf3atov3 140 0x17 (0x37) tifr2 - - - - -ocf2b ocf2atov2 162 0x16 (0x36) tifr1 - -icf1 - -ocf1b ocf1atov1 139 0x15 (0x35) tifr0 - - - - -ocf0b ocf0atov0 109 0x14 (0x34) reserved - - - - - - - - 0x13 (0x33) reserved - - - - - - - - 0x12 (0x32) reserved - - - - - - - - 0x11 (0x31) reserved - - - - - - - - 0x10 (0x30) reserved - - - - - - - - 0x0f (0x2f) reserved - - - - - - - - 0x0e (0x2e) reserved - - - - - - - - 0x0d (0x2d) reserved - - - - - - - - 0x0c (0x2c) reserved - - - - - - - - 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 92 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 92 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 92 0x08 (0x28) portc portc7 portc6 portc 5 portc4 portc3 portc2 portc1 portc0 92 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 92 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 92 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 91 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 91 0x03 (0x23) pinb pinb7 pinb6 pinb 5 pinb4 pinb3 pinb2 pinb1 pinb0 91 0x02 (0x22) porta porta7 porta6 porta 5 porta4 porta3 porta2 porta1 porta0 91 0x01 (0x21) ddra dda7 dda6 dda 5 dda4 dda3 dda2 dda1 dda0 91 0x00 (0x20) pina pina7 pina6 pina 5 pina4 pina3 pina2 pina1 pina0 91 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
14 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 8. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc znone4 call k direct subroutine call pc knone5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2
15 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 mnemonics operands description operation flags #clocks
16 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
17 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9. ordering information 9.1 atmega164a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega164a-au atmega164a-aur (5) atmega164a-pu atmega164a-mu atmega164a-mur (5) atmega164a-mch (4) atmega164a-mchr (4)(5) atmega164a-cu atmega164a-cur (5) 44a 44a 40p6 44m1 44m1 44mc 44mc 49c2 49c2 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn) 44mc 44-lead (2-row staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm exposed pad, quad flat no-lead package (qfn) 49c2 49-ball, (7 x 7 array) 0.65 mm pitch, 5 x 5 x 1 mm, very thin, fine-pitch ball grid array package (vfbga)
18 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.2 atmega164pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega164pa-au atmega164pa-aur (5) atmega164pa-pu atmega164pa-mu atmega164pa-mur (5) atmega164pa-mch (4) atmega164pa-mchr (4)(5) atmega164pa-cu atmega164pa-cur (5) 44a 44a 40p6 44m1 44m1 44mc 44mc 49c2 49c2 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn) 44mc 44-lead (2-row staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm exposed pad, quad flat no-lead package (qfn) 49c2 49-ball, (7 x 7 array) 0.65 mm pitch, 5 x 5 x 1 mm, very thin, fine-pitch ball grid array package (vfbga)
19 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.3 atmega324a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega324a-au atmega324a-aur (5) atmega324a-pu atmega324a-mu atmega324a-mur (5) atmega324a-mch (4) atmega324a-mchr (4)(5) atmega324a-cu atmega324a-cur (5) 44a 44a 40p6 44m1 44m1 44mc 44mc 49c2 49c2 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn) 44mc 44-lead (2-row staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm exposed pad, quad flat no-lead package (qfn) 49c2 49-ball, (7 x 7 array) 0.65 mm pitch, 5 x 5 x 1 mm, very thin, fine-pitch ball grid array package (vfbga)
20 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.4 atmega324pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. nipdau lead finish. 5. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega324pa-au atmega324pa-aur (5) atmega324pa-pu atmega324pa-mu atmega324pa-mur (5) atmega324pa-mch (4) atmega324pa-mchr (4)(5) atmega324pa-cu atmega324pa-cur (5) 44a 44a 40p6 44m1 44m1 44mc 44mc 49c2 49c2 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn) 44mc 44-lead (2-row staggered), 5 x 5 x 1.0 mm body, 2.60 x 2.60 mm exposed pad, quad flat no-lead package (qfn) 49c2 49-ball, (7 x 7 array) 0.65 mm pitch, 5 x 5 x 1 mm, very thin, fine-pitch ball grid array package (vfbga)
21 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.5 ATMEGA644A notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. taper & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v ATMEGA644A-au ATMEGA644A-aur (4) ATMEGA644A-pu ATMEGA644A-mu ATMEGA644A-mur (4) 44a 44a 40p6 44m1 44m1 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn)
22 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.6 atmega644pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. taper & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega644pa-au atmega644pa-aur (4) atmega644pa-pu atmega644pa-mu atmega644pa-mur (4) 44a 44a 40p6 44m1 44m1 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, thermall y enhanced plastic very thin quad flat no-lead (vqfn)
23 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.7 atmega1284 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega1284-au atmega1284-aur (4) atmega1284-pu atmega1284-mu atmega1284-mur (4) 44a 44a 40p6 44m1 44m1 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, quad flat no-lead/micro lead frame package (qfn/mlf)
24 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 9.8 atmega1284p notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc see ?speed grades? on page 335 . 4. tape & reel. speed (mhz) (3) power supply ordering code (2) package (1) operational range 20 1.8 - 5.5v atmega1284p-au atmega1284p-aur (4) atmega1284p-pu atmega1284p-mu atmega1284p-mur (4) 44a 44a 40p6 44m1 44m1 industrial (-40 o c to 85 o c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-pin, 0.600? wide, plastic dual inline package (pdip) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, quad flat no-lead/micro lead frame package (qfn/mlf)
25 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 10. packaging information 10.1 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 44a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
26 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 10.2 40p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
27 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 10.3 44m1 title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 44m1 zws h 44m1, 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, 5.20 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 9/26/08 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 0.20 ref b 0.18 0.23 0.30 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd-3. top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a3 a seating plane pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 1 2 3
28 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 10.4 44mc title dra wing no . rev . packa g e drawin g contact: packagedrawings@atmel.com 44mc a 9/13/07 d2 e2 l l b15 a18 b11 a13 b10 a12 b6 a7 a6 b5 b1 b20 a1 a24 et l b r0.20 0.40 er a19 b16 et/2 s ide view a1 a y c d e pin 1 id top view bottom view note: 1. the terminal #1 id is a laser-marked feature . common dimen s ion s (unit of measure = mm) s ymbol min nom max n o t e a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.23 0.30 c 0.20 ref d 4.90 5.00 5.10 d2 2.55 2.60 2.65 e 4.90 5.00 5.10 e2 2.55 2.60 2.65 et ? 0.70 ? er ? 0.40 ? k 0.45 ? ? l 0.30 0.35 0.40 y 0.00 ? 0.075 44mc, 44qfn (2-row staggered), 5 x 5 x 1.00 mm body, 2.60 x 2.60 mm exposed pad, quad flat no lead package
29 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 10.5 49c2 title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 49c2 cbd a 49c2, 49-ball (7 x 7 array), 0.65 mm pitch, 5.0 x 5.0 x 1.0 mm, very thin, fine-pitch ball grid array package (vfbga) 3/14/08 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a ? ? 1.00 a1 0.20 ? ? a2 0.65 ? ? d 4.90 5.00 5.10 d1 3.90 bsc e 4.90 5.00 5.10 e1 3.90 bsc b 0.30 0.35 0.40 e 0.65 bsc top view s ide view a1 ball id g f e d c b a 12 3 4 5 6 7 a a1 a2 d e 0.10 e1 d1 49 - ? 0.35 0.05 e a1 ball corner bottom view b e
30 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 11. errata 11.1 errata for atmega164a 11.1.1 rev. e no known errata. 11.2 errata for atmega164pa 11.2.1 rev. e no known errata. 11.3 errata for atmega324a 11.3.1 rev. f no known errata. 11.4 errata for atmega324pa 11.4.1 rev. f no known errata. 11.5 errata for ATMEGA644A 11.5.1 rev. f no known errata. 11.6 errata for atmega644pa 11.6.1 rev. f no known errata. 11.7 errata for atmega1284 11.7.1 rev. b no known errata. 11.8 errata for atmega1284p 11.8.1 rev. b no known errata.
31 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 12. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 12.1 rev. 8272c - 06/11 12.2 rev. 8272b - 05/11 1. updated ?atmega1284p dc characteristics? on page 334 . 1. added atmel qtouch library support and qtouch sensing capability features. 2. replaced figure 1-1 on page 2 by an updated ?pinout? that includes timer/counter3. 3. replaced figure 7-1 on page 10 by an updated ?block diagram of the avr architecture? that includes timer/counter3. 4. added ?rampz ? extended z-pointer register for elpm/spm (1) ? on page 15 . 5. added ?prr1 ? power reduction register 1? on page 49 . 6. renamed prr to ?prr0 ? power reduction register 0? on page 48 . 7. updated ?pcifr ? pin change interrupt flag register? on page 69 . pcicr replaces eimsr in the pcif3, pcif2, pcif1 and pcif0 bit description. 8. updated ?pcmsk3 ? pin change mask register 3? on page 70 . pcie3 replaces pcie2 in the bit description. 9. updated ?alternate functions of port b? on page 82 to include timer/counter3 10. updated ?alternate functions of port d? on page 88 to include timer/counter3 11. added ?tcnt3h and tcnt3l ?timer/counter3? on page 136 12. added ?ocr3ah and ocr3al ? output com pare register3 a? on page 137 13. added ?ocr3bh and ocr3bl ? output com pare register3 b? on page 137 14. added ?timsk3 ? timer/counter3 interr upt mask register? on page 139 15. updated all ?spi ? serial peripheral interface? ?register description? to reflect atmega1284 and atmega1284p. 16. updated ?addressing the flash during self-programming? on page 284 to include rampz register. 17. updated table 27-16 on page 314 . t wd_eeprom is 3.6ms instead of 9ms. 18. bods and bodse bits denoted as r/w 19. description of external pin modes below table 16-9 removed. 20. updated ?register summary? on page 10 to include timer/counter3. 21. updated the datasheet with atmel new style guide.
32 8272cs?avr?06/11 atmega164a/pa/324a/pa/644a/pa/1284/p 12.3 rev. 8272a - 01/10 1. initial revision (based on atmega164pa/324pa/644pa/1284p datasheet 8252g-avr-11/09 and on atmega644 datasheet 2593n-avr-09/09). 2. changes done: ? non-picopower devices added: atmega164a/324a/644a/1284 ? updated table 2-1 on page 7 ? updated table 10-1 on page 42 ? updated ?sleep modes? on page 42 and ?bod disable (1) ? on page 43 ? updated ?register description? on page 67 ? updated ?usart? on page 174 and ?usart in spi mode? on page 201 ? updated ?signature bytes? on page 300 and ?page size? on page 300 ? added ?dc characteristics? on page 329 for non-picopower devices. ? added ?atmega164a typical characteristics? on page 345 ? added ?atmega324a typical characteristics? on page 397 ? added ?ATMEGA644A typical characteristics? on page 449 ? added ?atmega1284 typical characteristics? on page 501 ? added ?ordering information? on page 17 for non-picopower devices ? added ?errata for atmega164a? on page 30 ? added ?errata for atmega324a? on page 30 ? added ?errata for atmega644pa? on page 30 ? added ?errata for atmega1284? on page 30
8272cs?avr?06/11 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel : (+81)(3) 3523-3551 fax : (+81)(3) 3523-7581 ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , qtouch ? , qmatrix ? , avr studio ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. windows ? and others are registered trademarks of microsoft corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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